2009.11.16作業

module top;
wire [3:0]x_in;
system_clk #50 clkl(x_in[0]);
system_clk #100 clkl(x_in[1]);
system_clk #200 clkl(x_in[2]);
system_clk #400 clkl(x_in[3]);
and4_algo c1 (y_out,x_in);
endmodule


module and4_algo(y_out,x_in);
input[3:0] x_in;
output y_out;
reg y_out;
integer k;
always@(x_in)
begin:and_loop
y_out=1;
for(k=0;k<=3;k=k+1)
if(x_in[k]==0)
begin
y_out=0;
disable and_loop;
end
end
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule