2009.10.26作業

module top;
wire a1,a0,b1,b0;
system_clk #50 clkl(b0);
system_clk #100 clkl(b1);
system_clk #200 clkl(a0);
system_clk #400 clkl(a1);
comparator c1(a1,a0,b1,b0,a_lt_b,a_gt_b,a_eq_b);
endmodule

module comparator (a1,a0,b1,b0,a_lt_b,a_gt_b,a_eq_b);
output a_lt_b,a_gt_b,a_eq_b;
input a1,a0,b1,b0;
assign a_lt_b = ({a1,a0}<{b1,b0}); assign a_gt_b = ({a1,a0}>{b1,b0});
assign a_eq_b = ({a1,a0}=={b1,b0});
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule