2009.10.26作業

module top;
wire a1,a0,b1,b0;
system_clk #50 clkl(b0);
system_clk #100 clkl(b1);
system_clk #200 clkl(a0);
system_clk #400 clkl(a1);
comparator c1(a1,a0,b1,b0,a_lt_b,a_gt_b,a_eq_b);
endmodule

module comparator (a1,a0,b1,b0,a_lt_b,a_gt_b,a_eq_b);
output a_lt_b,a_gt_b,a_eq_b;
input a1,a0,b1,b0;
assign a_lt_b = ({a1,a0}<{b1,b0}); assign a_gt_b = ({a1,a0}>{b1,b0});
assign a_eq_b = ({a1,a0}=={b1,b0});
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

2009.10.12作業

module top;
integer icin,ia,ib;
reg a,b,cin;
wire cout,s;
xor x1(s1,a,b);
and a1(c1,a,b);
xor x2(s,s1,cin);
and a2(c2,s1,cin);
xor x2(cout,c2,c1);
initial
begin
for(ia=0;ia<=1;ia=ia+1)
begin
cin=ia;
for(ib=0;ib<=1;ib=ib+1)
begin
a=ib;
begin
for(icin=0;icin<=1;icin=icin+1)
begin
b=icin;
#10 $display("a=%d b=%d cin=%d s=%d cout=%d",a,b,cin,s,cout);
end
end
end
end
end
endmodule

2009.10.05練習

module top;
integer ia,ib;
reg a,b;
wire c,s;
and a1(c,a,b);
xor x1(s,a,b);
initial
begin
for(ia=0;ia<=1;ia=ia+1)

begin

a=ia;

for(ib=0;ib<=1;ib=ib+1)

begin

b=ib;

#10 $display("a=%d b=%d c=%d",a,b,c);

end

end

end

endmodule