2009.09.28練習

module top;

integer ia,ib;

reg a,b;
wire c;
xor x1(c,a,b);
initial
begin
for(ia=0;ia<=1;ia=ia+1)

begin

a=ia;

for(i=0;ib<=1;ib=ib+1)

begin

b=ib;

#10 $display("a=%d b=%d c=%d",a,b,c);

end

end

end

endmodule

2009.09.21 練習

module top;
wire a,b;
reg c;
system_clock#100 clock1(a);
system_clock#50 clock2(b);
always
#1 c=a&b;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always begin #(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule